Institutional system dynamics speed regulation experiment table

Institutional system dynamics speed regulation experiment table,DSP system tr--ning desk

This experimental desk is used by motor motor to cont--n transmission. The mechanical system, including the workplace of the crank slider mechanism, is used for the stable operating state of the mechanical principles in the mechanical principles. Essence Use advanced experimental technical methods such as sensors and computers to conduct experimental operations, and tr--n modernized experimental test methods and methods to enhance engineering practical ability.

Experimental project content:

1. Mechanical speed fluctuation test simulation experiment:

Observe the speed fluctuations of mechanical mechanical and solve the unevenness of the system's operation. Adjust the motor speed, observe the speed fluctuation phenomenon at different speeds, and compare the actual measurement and simulation curve.

2. Mechanical speed fluctuation adjustment experiment:

Change the size of the flywheel, observe the change of mechanical speed fluctuations, and compare the analysis of the theoretical calculation results.

M--n technical features:

1. The launching of the crank block mechanism uses a special crankshaft and connecting rod. It has strict ideas and exquisite design to ensure that each motion component of the experimental table has a good cooperation gap, beautiful appearance, convenient operation, and long service life.

2. The experimental table consists of m--n components such as machine seats, DC speed regulating motors, belt transmission devices and crank sliders. The crankshaft 1-End with an angle displacement sensor, and a flywheel in addition.

Institutional system dynamics speed regulation experiment table,DSP system tr--ning desk

1. System summary:

The DSP experimental box can use the TMS320VC54XX chip of the Texas Instrument (TI) as the m--n processor (CPU), such as 5402, 5409, 5410, 5416 and other chips; the Cyclone series FPGA chip of Altera, such as EP1C3, can also be used. The implementation of various algorithms that can be used to achieve digital signal processing fully meet the requirements of teaching experiments and secondary development. This product m--nly includes extended connectors, system clocks, timers, HPI interfaces, standard serial ports, high -speed AD/DA conversion, voice input and output interface circuits (AD50), dual -sound tone changes to DTMF frequency frequency of DTMF frequency frequency. The generator, traffic light module, DC motor drive module (can achieve closed -loop control), step motor drive module, keyboard processing, LCD LCD display, I/O input output module, DSP processor and 51 series processor communication. This product is more suitable for control occasions such as voice processing, frequency frequency control, drag system, and portable detection equipment.

2. M--n functions:

M--n processor:

1. TMS320VC5402.

2. Altera FPGA chip: Cyclone EP1C3

Internal memory: internal double -port memory of 16KX16bit, 4K inner ROM, external program/data memory expansion: 64kx16bit data memory of the w--ting cycle, 64kx16bit program memory; EPROM memory loaded automatically in 32KX8BIT system; 256K X16bit Flash memory. Voice input and amplifier output: AD \ DA (TMS320AD50C) with 16 -bit synchronous buffer mouth, ** sampling frequency is 22.05k. There is a hardware filtering function, with microphone input and speaker output function. UART serial interface: The 16C550C chip is used to meet the RS232 standard. Keyboard processing: 4X8 keyboard controlled by Lattice 1016. LCD LCD display: 128x64 graphics LCD. High -speed AD/DA conversion: TLC7528, TLV1571.